1. Field of the Invention
The present invention generally relates to the design of semiconductor chips and integrated circuits, and more particularly to the use of cloning techniques to manage timing requirements in an integrated circuit design.
2. Description of the Related Art
Integrated circuits are used for a wide variety of electronic applications, from simple devices such as wristwatches, to the most complex computer systems. A microelectronic integrated circuit (IC) chip can generally be thought of as a collection of logic cells with electrical interconnections between the cells, formed on a semiconductor substrate (e.g., silicon). An IC may include a very large number of cells and require complicated connections between the cells. A cell is a group of one or more circuit elements such as transistors, capacitors, resistors, inductors, and other basic circuit elements grouped to perform a logic function. Cell types include, for example, core cells, scan cells and input/output (I/O) cells. Each of the cells of an IC may have one or more pins, each of which in turn may be connected to one or more other pins of the IC by wires. The wires connecting the pins of the IC are also formed on the surface of the chip. For more complex designs, there are typically at least four distinct layers of conducting media available for routing, such as a polysilicon layer and three metal layers (metal-1, metal-2, and metal-3). The polysilicon layer, metal-1, metal-2, and metal-3 are all used for vertical and/or horizontal routing.
An IC chip is fabricated by first conceiving the logical circuit description, and then converting that logical description into a physical description, or geometric layout. This process is usually carried out using a netlist, which is a record of all of the nets, or interconnections, between the cell pins. A layout typically consists of a set of planar geometric shapes in several layers. The layout is then checked to ensure that it meets all of the design requirements, particularly timing requirements. The result is a set of design files known as an intermediate form that describes the layout. The design files are then converted into pattern generator files that are used to produce patterns called masks by an optical or electron beam pattern generator. During fabrication, these masks are used to pattern a silicon wafer using a sequence of photolithographic steps. The process of converting the specifications of an electrical circuit into a layout is called the physical design.
Cell placement in semiconductor fabrication involves a determination of where particular cells should optimally (or near-optimally) be located on the surface of a integrated circuit device. Due to the large number of components and the details required by the fabrication process for very large scale integrated (VLSI) devices, physical design is not practical without the aid of computers. As a result, most phases of physical design extensively use computer-aided design (CAD) tools, and many phases have already been partially or fully automated. Automation of the physical design process has increased the level of integration, reduced turn around time and enhanced chip performance. Several different programming languages have been created for electronic design automation (EDA), including Verilog, VHDL and TDML. A typical EDA system receives one or more high level behavioral descriptions of an IC device, and translates this high level design language description into netlists of various levels of abstraction.
Physical synthesis is prominent in the automated design of integrated circuits such as high performance processors and application specific integrated circuits (ASICs). Physical synthesis is the process of concurrently optimizing placement, timing, power consumption, crosstalk effects and the like in an integrated circuit design. This comprehensive approach helps to eliminate iterations between circuit analysis and place-and-route. Physical synthesis has the ability to repower gates (changing their sizes), insert repeaters (buffers or inverters), clone gates or other combinational logic, etc., so the area of logic in the design remains fluid. However, physical synthesis can take days to complete, and the computational requirements are increasing as designs are ever larger and more gates need to be placed. There are also more chances for bad placements due to limited area resources.
Faster performance and predictability of responses are elements of interest in circuit designs. As process technology scales to the submicron regime, interconnect delays increasingly dominate gate delays. Consequently, physical design optimization tools such as floorplanning, placement, and routing are becoming more timing-driven than the previous generation of tools. Different optimization techniques are used to fix bad timing behaviors during physical synthesis. Cloning is an optimization technique that can fix some timing problems that other optimization techniques (buffer insertion, repowering) cannot. Cloning takes an original gate and duplicates it for use with a portion of the circuit. The inputs of the original gate and the duplicate are the same.
A simplified cloning example is illustrated in FIGS. 1A and 1B. Circuit 2 of FIG. 1A includes two inputs (sources) 4a, 4b, an OR gate 6, and two outputs (sinks) 8a, 8b. The sources and sinks may be latches. In this example the location of OR gate 6 is fixed. The numbers “1” and “3” are the delay values for those segments of the circuit. Due to the location of OR gate 6 closer to sink 8a, the slack at sink 8a (the difference between the actual propagation time and the maximum allowable time) is 1, while the slack at sink 8b is −1. A negative slack value indicates that the signal will actually arrive after its required arrival time, i.e., a timing violation. As seen in FIG. 2B, cloning solves this violation by adding another OR gate 6′ to create a modified circuit 2′ wherein each gate 6, 6′ receives inputs from both sources 4a, 4b, but gate 6 provides an output only to sink 8a while gate 6′ provides an output to sink 8b and is located closer to sink 8b. The result is the same (positive) slack for both sinks.
Timing closure is an important problem for ASIC and server designs with 90 nm technology and beyond. While cloning is useful for solving some timing problems, it is not particularly efficient. Prior art cloning uses gate delay models (the delay through a gate is proportional to the total capacitances of gates which it drives), ignoring the interconnect delay and physical layout information, and does not determine an optimum location of the duplicated gate. For example, if the cloned gate 6′ in FIG. 1B had been placed too near the original gate 6, the net would still exhibit poor slack. Existing cloning techniques have difficulty even determining a good partition where there are many sinks in the net. It would, therefore, be desirable to devise a cloning method which provided improved timing closure. It would be further advantageous if the improved cloning method could achieve optimal timing with high computational efficiency.